There are a variety of different types of integrated circuits. One common type of integrated circuit is known as a programmable logic device (PLD), and can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth. Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
One danger to any type of IC, including the PLDs mentioned above, is potential damage from static electricity. More specifically, during physical handling of any IC before it is electrically coupled to and becomes part of a larger circuit, circuitry within the IC can potentially be damaged by static electricity carried by anything that happens to come into physical contact with one of the externally-accessible pads or terminals that are electrically coupled to the circuitry within the IC. For example, the human body can carry a charge of static electricity on the surface of the skin. If a finger happens to briefly touch one of the pads, static electricity on the skin could potentially cause a spike of current to flow into the IC through that pad, and that spike of electrostatic discharge (ESD) current could potentially burn out or otherwise damage part or all of the circuit within the IC.
In order to help protect an IC from damage due to ESD, it is known to supplement the main circuit in the IC with some special additional ESD circuitry that is specifically configured to absorb spikes of ESD current. However, for the ESD circuitry to be effective, electrically conductive paths between pads and the ESD circuit elements should have a very low resistance. Otherwise, when a spike of ESD current enters the IC through one of the pads, it will be less likely to travel from the pad to an ESD element, and more likely to travel to and damage the main circuit. Consequently, after an IC has been designed, and before it is actually fabricated, it is desirable to verify that, for each of the pads, a path from that pad to at least one ESD element has a path resistance below a specified value, such as 1 ohm (Ω).
A pre-existing approach uses a manual direct current (DC) simulation. A person extracts an entire network or “net” from an IC design, and runs a DC simulation to determine the voltage drop from a pad to an ESD element. Then, by applying Ohm's law (V=IR), the resistance of that path can be determined. This manual evaluation has to be repeated for every ESD path in the IC. Although this pre-existing approach has been generally adequate for its intended purposes, it has not been entirely satisfactory in all respects, due in part to the fact that it is inherently very tedious and time consuming.